Successful applicants will be trained for one or more of the following tasks:
Development of IC layout verification rules and tools to ensure quality of IC physical layout based on the fabrication technology used.
Development of parametrized cell libraries and tools for use and in aid of IC physical layout design automation
Development of automation scripts for simulation and optimization of automated placement of logic cells and automated routing of wiring connections in IC Logic blocks
A degree in Electronics and Communications Engineering. Computer Engineering, or Information and Communications Technology.
Above average academic credentials specifically in electronics and programming courses.
A good understanding in analog and digital circuits (discrete and logic-gate devices).
A proficiency in any programming languages, specifically in: C++, Visual Basic, Perl, or Unix shell scripting.
An interest and willingness to pursue a career in the development of EDA Tools for: IC CAD Layout, IC Layout Verification, or IC Layout Automation.
Interested applicants may email their application letter, comprehensive resume with photo, transcript of records, and other supporting documents to firstname.lastname@example.org
. Indicate “Programmer Trainee/Assistant Layout Engineer (IC Mask Design)” in the subject.