Xilinx PLL and DCM

[drei_0958]

guys pa help naman po jan kung sino ang marunong sa Xilinx.
nahihirapan kasi ako gumamit ng Xilinx.
bale ganito

I have an FPGA project and already done coding RTL in Verilog.
The problem is di ko alam gumamit ng PLL at DCM sa Xilinx.
Sa Altera ako kasi sanay.
Bale sa altera makakapag generate ka ng any clock signal from PLL using your
system clock by using  M/D.
Di ko nakita sa PLL at DCM ng Xilinx yun
Patulong naman po mga boss

I have to generate  clocks from the PLL or DCM using one system clock
system clock = 60MHz <---- galing sa crystal oscillator
I2C Clock (fast mode)  =3.6MHz
I2C Clock (high speed mode) = 13.6MHz
SPI Clock        = 50MHz
UART Clock     = 19.2kHz

pa help po T_T
 

[motion55]

Give some more info, like what FPGA family you are using.

Use the core generator to generate a DCM component.

From the menu, select Tools -> Core Generator.

Within the Core Generator, select the FPGA Features and Design folder and within that folder select Clocking...

Tapos modify the features of the DCM to suit your clocking requirements. Make sure you locate your clock on the I/O bank with a DCM.

[drei_0958]

Device Family: Spartan 6
Device           : XC6LX45
Package         : CSG324



salamat sa reply.
I have a question regarding to this

ganun ba talaga ang setting ng wizard nya?
kapag nagmultiply ka lahat ng clock out na mumultiply din.
hindi ba puede ang individual multiply ng clock??
sa quartus ( for altera) kasi puede mo i multiply ang output ng pll mo
individually.

as you can see apat ang dapat kong i generate na clock
they dont have a common multiple T_T.

can you give some tips paano ko magegenerate yung apat na clock ko since
ang allowed ata sa dcm pll ng xilinx eh multiply all clock out lang


salamaT!!!!!

[motion55]

Kailangan ba exact ang clock values? AFAIK, none of them require an exact frequency value. I.E. all of them will still work within a loose tolerance. You can use the DCM to produce the highest possible clock and divide this down to the closest value each will need.

[motion55]

Di pa ako nakagamit ng Spartan 6 but you can consult the Spartan-6 FPGA Clocking Resources User Guide for more tips.

http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

[drei_0958]

ah so di pala necessary saktong clock frequency

[drei_0958]

sir na try ko na po yung clocking wizard kaso mabagal yung isang clock ko
19.2KHz lang. nag eeror yung wizard kasi di nya madetermine yun m/d kasi nga maliit yung
isang clock..

possible ba gumamit ng isa pang dcm allowed ba ito?

salamat po sa reply

[motion55]

Pwede gumamit ng dalawa or more DCMs, kung available but...

Normally di gigagamit ng DCM to directly generate 19.2KHz. Use Verilog or VHDL to divide down the output from the DCM down to the frequency needed by the UART, (usually 16x 19.2Khz).

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