Hello World using E-gizmo's CPLD board

[marcelino]

hello!

eto ang pinaka una kong actual implementation on CPLD. kaya, super happy ako!!!

The E-Gizmo's CPLD board make use of XC2C128 CoolRunner-II CPLD from Xilinx and is provided a jtag programmer which is connected through the parallel port. However,  board does not have clock source, so I have to provide. Buti nalang at may DS32khz ako... bigay pa to saakin ni electron ...long ago! The good thing about the DS32Khz IC is that, it provides clock in the voltage range of the CPLD chip that is only up to 3.6V. and Voltage high sa output ng DS32Khz is 2.4V - still in the range of HIGH level input for any I/o pin of XC2C128 CoolRunner-II CPLD (2-3.9V).

anyway, here is a very simple program, THE HELLO WORLD!

Code: [Select]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity delayed is
    Port ( clock : in  STD_LOGIC;
           LED : out  STD_LOGIC);
end delayed;

architecture Behavioral of delayed is

begin
process(clock)
variable clockDelay : integer range  0 to 10000 := 0; --tsamba lang yung range
begin
if clock'event and clock = '1' then
clockDelay := clockDelay + 1; --increment the delay
if clockDelay = 0 then
LED <= '1';
elsif clockDelay = 5000 then
LED <= '0';
end if;
end if;
end process;

end Behavioral;


['yus]

ano'ng advantage(s) ng CPLD over sa microcontroller(e.g. PIC) ?

 walang parallel port ang pc ko

[marcelino]

ano'ng advantage(s) ng CPLD over sa microcontroller(e.g. PIC) ?

 walang parallel port ang pc ko

kung gusto mong mag-implement ng mga digital circuits mas mabilis to. combinational circuits like alu, multiplexers, adder , comparator , adder also yung lahat ng mga lathes/flipflops and basic digital logic ay pwedeng ilagay sa loob... kaya typically, high pins count ang CPLDs and FPGA.

also, even those ports/interfaces like UART, I2C, SPI, etc... could be emulated in a CPLD/FPGA.

depende sa clock source, pwede mag-operate yang particular chip na yan to 250Mhz.

and lastly, concurrent ang operations...


di ko lang alam, kung napawork ni sir RD yung ftdi chip na parallel... last year na ipost nya yun.

[rdpzycho]

hindi ko pa natapos sis marce. meron kasing isang project na nanggulo sa amin. pero meron na akong sample circuit galing sa ARM programmer.

tama si sis marce, for CPLD/FPGA, sa isang cycle pwedeng gawin ang input1 x input2, input3 x input 4, input5 x input6, etc. sa MCU, tig-iisang cycle sila. 'yung mga nangangailangan ng parallel computing sa DSP na mahirap implement sa multi-core, pwedeng pwedeng gawin sa FPGA.

hindi ko pa nasusubukan 'yung FPGA. lagi na lang akong walang time. nami-miss ko na ring mag-program. hehehe.

[paranz]

ayus, galing mo sis marce..

Sana magawa ko after sem ends

[subzer0]

nice ate marce!!!ipon muna ako para makabili,yung program po VHDL based?parang PASCAL language,anu anu po kaya pwedeng gawin sa kit na ito?

[marcelino]

nice ate marce!!!ipon muna ako para makabili,yung program po VHDL based?parang PASCAL language,anu anu po kaya pwedeng gawin sa kit na ito?

hmmmmmmm.. madami!!! hheheh

controllers, kahit ano! namention ko nga earlier, pwede mong maemulate ang kahit anong interfacing protocols (UART, I2C, SpI, etc...)

[subzer0]

hmmmmmmm.. madami!!! hheheh

controllers, kahit ano! namention ko nga earlier, pwede mong maemulate ang kahit anong interfacing protocols (UART, I2C, SpI, etc...)

ok na ok to,pwede kayang gawing DIY oscilloscope ito?baka mas maganda itong gamitin compared sa mga DSP chips.

[rdpzycho]

'yung mga USB based scope, FPGA ang gamit.

[paranz]

i would really recommend na gamitin ang kit na ito sa logic circuit class dito sa school. This the next step in technology for us after microcontroller, kaya natural na ito ang next sa learning path ko.

[rdpzycho]

maganda nga 'to sa logic circuits lalo na kung merong mga medyo complex designs. implementation of multipliers, division, and MAC (multiply-accumulate) mas mabilis ma-appreciate dahil sandali lang magagawa na, sa actual IC, baka hindi pa gumana. hehehe.

though hindi 'to dapat sa MCU class dahil magkaiba sila ng discipline. meron ata kasing prof na gusto 'tong ituro sa MCU class niya.

[marcelino]

eto pa...

A HEX COUNTER DEMONSTRATION

this time i make use of modular presentation, that if looked at RTL (register transfer level), there will be three modules. These modules are Delay, COunter and the converter. the schematic presentation of the RTL is shown in the figure:


and if look inside that RTL,

Code: [Select]

-- DELAY CODES --
-- set to 2Hz --
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity delay is
    Port ( clock_osc : in  STD_LOGIC;
           clock_out : out  STD_LOGIC);
end delay;

architecture Behavioral of delay is

begin
process(clock_osc)
variable counter: integer range 0 to 32768 :=0;
--1sec = 32768 cycles
--32768/4 = 8192 = 4Hz
--32768/2 = 16384 = 2Hz
begin
if clock_osc ='1' and clock_osc'event then
counter := counter + 1;
if counter = 0 then
clock_out <= '1';
elsif counter = 16384 then
clock_out <= '0';
end if;
end if;
end process;
end Behavioral;

-----------------------------------------------------------
-- COUNTER CODE --
-- increments each tick of the clock --
-- outputs a 4bit counter, that is from 0x00 - 0x0F --
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter is
    Port ( clock : in  STD_LOGIC;
           count : out  STD_LOGIC_VECTOR (3 downto 0));
end counter;

architecture Behavioral of counter is

signal counter : std_logic_vector (3 downto 0);

begin

process (clock)

begin

if clock='1' and clock'event then
if counter = "1111" then
counter <= "0000";
else
counter <= counter + 1;
end if;
end if;
end process;

count <= counter;
end Behavioral;

------------------------------------------------------------
-- CONVERTER CODE --
-- converts the output from counter [3:0] to LED output[6:0]
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity converter is
    Port ( count_in : in  STD_LOGIC_VECTOR (3 downto 0);
           LED : out  STD_LOGIC_VECTOR (6 downto 0));
end converter;

architecture Behavioral of converter is

begin
with count_in select
-- abcdefg
LED <= "0110000" when "0001", --1
"1101101" when "0010", --2
"1111001" when "0011", --3
"0110011" when "0100", --4
"1011011" when "0101", --5
"1011111" when "0110", --6
"1110000" when "0111", --7
"1111111" when "1000", --8
"1111011" when "1001", --9
"1110111" when "1010", --A
"0011111" when "1011", --b
"1001110" when "1100", --C
"0111101" when "1101", --d
"1001111" when "1110", --E
"1000111" when "1111", --F
"1111110" when others; --0


end Behavioral;

-----------------------------------------------------------
-- TOP LEVEL VHDL DESGIN --
-- uses port mapping to connect the 3 modules...
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top is
    Port ( clock_32k : in  STD_LOGIC;
           LED_out : out  STD_LOGIC_VECTOR (6 downto 0));
end top;

architecture Behavioral of top is

component delay
Port ( clock_osc : in  STD_LOGIC;
           clock_out : out  STD_LOGIC);
end component;

component counter
Port ( clock : in  STD_LOGIC;
           count : out  STD_LOGIC_VECTOR (3 downto 0));
end component;

component converter
Port ( count_in : in  STD_LOGIC_VECTOR (3 downto 0);
           LED : out  STD_LOGIC_VECTOR (6 downto 0));
end component;

signal clock_delay : std_logic;
signal count_counter : std_logic_vector (3 downto 0);


begin
U1 : delay
port map (
clock_osc => clock_32k,
clock_out => clock_delay
);

U2 : counter
port map (
clock => clock_delay,
count => count_counter
);

U3 : converter
port map (
count_in => count_counter,
LED => LED_out
);

end Behavioral;



the short video:

[paranz]

^ logic design 1 and 2 and computer architecture subject lang pwede. Mas relevant ito lalo na sa Comp. engg students

[paranz]

btw, sis marce VHDL ba yung code or verilog?

[rdpzycho]

^ logic design 1 and 2 and computer architecture subject lang pwede. Mas relevant ito lalo na sa Comp. engg students

agree. maganda 'to sa mga simple ALU design or directly implementing the SAP-1 and SAP-2 computer. mas may feel ka sa tinuturo.

[marcelino]

btw, sis marce VHDL ba yung code or verilog?

VHDL sis...

di ko pa natatry ang verilog...
DLSU kasi ako nag-aral eh... hehehe

DLSU vhdl, ADMU verilog, UPD both!

[marcelino]

agree. maganda 'to sa mga simple ALU design or directly implementing the SAP-1 and SAP-2 computer. mas may feel ka sa tinuturo.

http://esd.cs.ucr.edu/labs/tutorial/
nadito ang mga samples ng VHDL codes for particular component...

yeah... i have already make use of VHDL to implement a modified SAP1. 16 instructions lang yata ang inilagay ko. pero di ko pa yung naiload sa real chip... spartan 3  yata yung ginamit kong target...

[paranz]

^ haay napakasarap talaga pag naituro na ito . In the meantime, aral muna ako. Imagine, in the next few years yung mga students natin hindi lang marunong magprogram ng MCU kundi kaya pa magdesign ng mga soft core CPUs. Astig ang pinoy!

[rdpzycho]

dami niyo na pala experience dito sis marce.

[marcelino]

dami niyo na pala experience dito sis marce.

di naman masyado... konti lang naman.