Hello World using E-gizmo's CPLD board

[0b00000111]

go!! galawin mo... ilipat mo na lalagyan! itabi mo sa mga panties mo! hehehe

yung CPLD ko din di ko pa nagagalaw, medyo marami pang ginagawa pero for sure gagamitin ko din yun

btw, ano mas magandang pag-aralan muna? VHDL o Verilog?

[glutnix_neo]

yung CPLD ko din di ko pa nagagalaw, medyo marami pang ginagawa pero for sure gagamitin ko din yun

btw, ano mas magandang pag-aralan muna? VHDL o Verilog?

sa aking pananaw mas maganda ang VHDL kasi standard yun although marami na rin nagsusupport ng verilog.

[marcelino]

sa tingin ko, kahit alin naman dyan. but personally, i din't like verilog kasi parang jumbled words lang... no offense sa verilog lovers. hehehe

I prefer VHDL, kasi yan yun una kong natutunan!

[ckiana02]

If you know how to program using c then go for verilog.  From experience (I teach both VHDL and Verilog), it is much easier to program in verilog however it is also easier to make mistakes using verilog.  VHDL is structured and has strict code checking.  So if you do not know how to program using c then go for VHDL :-)
 

[marcelino]

^sir sa tingin ko po, sanayan din. I know C before i studied VHDL. ngayon, VHDL ang tinuro sa school, kaya VHDL na din ako.
para po saakin, HDL in general (VHDL or Verilog ) is very easy to code when you already know C. Example po sa processes like IF-ELSE conditions... having to know C, you can easily grasp a sample code. Yung mga headers and initializations (instantiations) lang nalang ang poproblemahin - like entity, etc. Kung sa formatting naman, nagkakalat naman yun references sa internet so walang problema.

what I like most about HDL is even you use different IDE (like Quartus of Altera and ISE of Xilinx), the code could still work. Very standard. sabagay, medyo bago palang naman ang VHDL standard.

will try Verilog din, someday.

[ckiana02]

Below are examples of verilog and VHDL codes.  These are equivalent codes for a circuit that counts 0 to 7 with synchronous clear.

Verilog

Code: [Select]

//circuit that counts 0 to 7 with clear in verilog
module cnt8(clk, clr, q);
input clk, clr;
output [2:0] q;

reg [3:0] q;
always @ (posedge clk)
  if (clr) q <= 0;
  else     q <= q + 1; 
         
endmodule
//end of cnt8 design


//test bench for cnt8
module tb();
reg clk, clr;
wire [2:0] q;

cnt8 uut(clk, clr, q);

initial
begin
 clk = 0; clr = 1;
 #30 clr = 0;
 #1000 $finish;
end

//40 ns clock generation
always #20 clk = !clk;

endmodule




VHDL

Code: [Select]

--circuit that counts 0 to 7 with clear in VHDL
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;

ENTITY cnt8 IS
  PORT( clr, clk : IN std_logic;
               q : OUT std_logic_vector (2 downto 0));
  END;

ARCHITECTURE logic OF cnt8 IS
SIGNAL tmp : std_logic_vector (2 downto 0);
BEGIN

   count: PROCESS (clr, clk)
   BEGIN
         IF (clr = '1') THEN
                  tmp <= "000";
         ELSIF (clk'EVENT and clk = '1') THEN
                  tmp <= tmp + 1;
          END IF;
    END PROCESS;
   
     q <= tmp;

END logic;
--end of cnt8 design

--test bench for cnt8
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
   
ENTITY cnt8test IS
END;

ARCHITECTURE testxxxx OF cnt8test IS
SIGNAL clk : std_logic := '0';
SIGNAL clr : std_logic := '1';
SIGNAL q : std_logic_vector (2 downto 0) ;

COMPONENT cnt8
  PORT( clr, clk : IN std_logic;
               q : OUT std_logic_vector (2 downto 0));
END COMPONENT; 

BEGIN
UUT: cnt8 PORT MAP (clr, clk, q);

--40 ns clock generation
PROCESS
BEGIN
  clk <= '0';
  wait for 20 ns;
  clk <= '1';
  wait for 20 ns;
END PROCESS;

--clear generation
PROCESS
BEGIN
    wait for 30 ns;
    clr <= '0';
END PROCESS;

END;






[celdricg]

di ko pa natry verilog at wala pa ako balak subukan yun.. VHDL muna tayo

[gentleman]

ako din vhdl din ang ginamit ko sa last project ko sa fpga. Question, magkano ang cpld board sa e-gizmo tsaka pahingi ng link di ko kasi makita eh. thanks

[marcelino]

ako din vhdl din ang ginamit ko sa last project ko sa fpga. Question, magkano ang cpld board sa e-gizmo tsaka pahingi ng link di ko kasi makita eh. thanks

http://www.e-gizmo.com/KIT/CPLD.htm

[gentleman]

http://www.e-gizmo.com/KIT/CPLD.htm

pogi point for you sir.
thanks

[0b00000111]

sisimulan ko na ito para magamit ko na ang CPLD kit ng e-gizmo

[0b00000111]

Below are examples of verilog and VHDL codes.  These are equivalent codes for a circuit that counts 0 to 7 with synchronous clear.

Verilog

Code: [Select]

//circuit that counts 0 to 7 with clear in verilog
module cnt8(clk, clr, q);
input clk, clr;
output [2:0] q;

reg [3:0] q;
always @ (posedge clk)
  if (clr) q <= 0;
  else     q <= q + 1; 
         
endmodule
//end of cnt8 design


//test bench for cnt8
module tb();
reg clk, clr;
wire [2:0] q;

cnt8 uut(clk, clr, q);

initial
begin
 clk = 0; clr = 1;
 #30 clr = 0;
 #1000 $finish;
end

//40 ns clock generation
always #20 clk = !clk;

endmodule




VHDL

Code: [Select]

--circuit that counts 0 to 7 with clear in VHDL
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;

ENTITY cnt8 IS
  PORT( clr, clk : IN std_logic;
               q : OUT std_logic_vector (2 downto 0));
  END;

ARCHITECTURE logic OF cnt8 IS
SIGNAL tmp : std_logic_vector (2 downto 0);
BEGIN

   count: PROCESS (clr, clk)
   BEGIN
         IF (clr = '1') THEN
                  tmp <= "000";
         ELSIF (clk'EVENT and clk = '1') THEN
                  tmp <= tmp + 1;
          END IF;
    END PROCESS;
   
     q <= tmp;

END logic;
--end of cnt8 design

--test bench for cnt8
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
   
ENTITY cnt8test IS
END;

ARCHITECTURE testxxxx OF cnt8test IS
SIGNAL clk : std_logic := '0';
SIGNAL clr : std_logic := '1';
SIGNAL q : std_logic_vector (2 downto 0) ;

COMPONENT cnt8
  PORT( clr, clk : IN std_logic;
               q : OUT std_logic_vector (2 downto 0));
END COMPONENT; 

BEGIN
UUT: cnt8 PORT MAP (clr, clk, q);

--40 ns clock generation
PROCESS
BEGIN
  clk <= '0';
  wait for 20 ns;
  clk <= '1';
  wait for 20 ns;
END PROCESS;

--clear generation
PROCESS
BEGIN
    wait for 30 ns;
    clr <= '0';
END PROCESS;

END;






mukhang kelangan ko din pag aralan mag code ng test bench sa VHDL para mas macustomize ko mga kailangan kong itest... right now kasi gamit ko yung wizard sa pag-gawa ng test bench using Xilinx ISE (pang tamad ba? hehe)..

ganda point sa iyo ckiana02 ...

[glutnix_neo]

hindi ko pa magrasp concept ng test bench, nalipat attention ko sa arduino, processing, at mobile processing eh,

tutorial naman master 7.

[0b00000111]

^^

sis glutnix basic na basic pa lang ang mga nalalaman ko nakakahiya pa magshare antayin natin si marcelina at ckiana02 para sa mga bagay bagay na yan madami din akong gustong malaman tungkol sa test bench na yan

[marcelino]

^^

sis glutnix basic na basic pa lang ang mga nalalaman ko nakakahiya pa magshare antayin natin si marcelina at ckiana02 para sa mga bagay bagay na yan madami din akong gustong malaman tungkol sa test bench na yan

wag mo naman ako sis asahan... heheh di naman ako magaling. may alam lang.

pero ganito ang pagkakaintindi ko ng testbech.
kung halimbawa, gumawa tayo ng isang program, for instance a 2-input AND gate (syempre may 1-output yan). Sa testbench, ilalagay mo ang lahat na possible test na gusto mo. for AND gate, syempre, 00, 01, 10 and 11. lalayan mo ito ng time component para makita mo sa simulation kung tama nga ang pagkakadesign mo ng 2-input AND gate.

sa example code ni sir ckiana02, counter with clear. kung maoobserbahan mo, yung entity nya

Code: [Select]

ENTITY cnt8 IS
  PORT( clr, clk : IN std_logic;
               q : OUT std_logic_vector (2 downto 0));
  END;may 2 inputs, clr and clk.

yung testbench, naggenerate ng input which is the clock and clear:

Code: [Select]

BEGIN
UUT: cnt8 PORT MAP (clr, clk, q);

--40 ns clock generation
PROCESS
BEGIN
  clk <= '0';
  wait for 20 ns;
  clk <= '1';
  wait for 20 ns;
END PROCESS;

--clear generation
PROCESS
BEGIN
    wait for 30 ns;
    clr <= '0';
END PROCESS;

END;





[0b00000111]

wow thanks... at isa pang tanong, STD_LOGIC ba kalimitang ginagamit? kasi may natesting ko, BIT yata yun iirc, ayaw magcompile ng Test Bench, pinalitan ko ng STD_LOGIC gumana na...

[marcelino]

wow thanks... at isa pang tanong, STD_LOGIC ba kalimitang ginagamit? kasi may natesting ko, BIT yata yun iirc, ayaw magcompile ng Test Bench, pinalitan ko ng STD_LOGIC gumana na...

ako sis, laging STD_LOGIC ang gamit ko. di pa ako nakakagamit ng BIT. siguro specific yung BIT sa include header.

Code: [Select]

USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
di ako sigurado nyan. pero di pa ako nakakakitang VHDL na may BIT.

[0b00000111]

ok, yung STD_LOGIC na din lagi kong gagamitin

[motion55]

USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;

If you "use" the above libraries, you can find the definition of STD_LOGIC in the files "std_logic_1164.vhd" and "std_logic_unsigned.vhd". In the file "std_logic_1164.vhd", you can also discover what operations are available if that file is "used".

Code: [Select]

    -------------------------------------------------------------------   
    -- logic state system  (unresolved)
    -------------------------------------------------------------------   
    TYPE std_ulogic IS ( 'U',  -- Uninitialized
                         'X',  -- Forcing  Unknown
                         '0',  -- Forcing  0
                         '1',  -- Forcing  1
                         'Z',  -- High Impedance   
                         'W',  -- Weak     Unknown
                         'L',  -- Weak     0       
                         'H',  -- Weak     1       
                         '-'   -- Don't care
                       );
    -------------------------------------------------------------------   
    -- unconstrained array of std_ulogic for use with the resolution function
    -------------------------------------------------------------------   
    TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic;
                                   
    -------------------------------------------------------------------   
    -- resolution function
    -------------------------------------------------------------------   
    FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;
   
    -------------------------------------------------------------------   
    -- *** industry standard logic type ***
    -------------------------------------------------------------------   
    SUBTYPE std_logic IS resolved std_ulogic;


On Xilinx ISE, the files are found in the "C:\Xilinx\11.1\ISE\vhdl\src\ieee\" path.

[ckiana02]

Medyo rusty na ako sa VHDL since I shifted to verilog 5 years ago :-).

BIT means logic 0 or 1 only (no high impedance, no undefined etc) as oppose to STD_LOGIC (as defined by motion 555).

BIT is precompiled into the library ”STD” (accessed via USE STD.STANDARD.ALL that is implicitely declared).
package standard is
type bit is (‘0’, ‘1’);

to explain the and example above i.e. making a testbench that will generate the input 00, 01, 10, 11 (cycles back) at an interval of 30 ns.

Code: [Select]

--this is a comment :-)

---------My_And
library ieee;
use ieee.std_logic_1164.all;

entity My_And is
  port(A, B  : in std_logic;
       ANDED : out std_logic);
end;

architecture BEHAVIOR of My_And is  

  ANDED <= A and B;      

end;
----------end of the circuit My_And

------------start of testbench
library ieee;
use ieee.std_logic_1164.all;

Entity testMy_And Is

end;

Architecture test Of testMy_And Is
Signal Ax : std_logic := '0'; --initial value of Ax
Signal Bx     : std_logic := '0'; --initial value of Bx
Signal ANDout : std_logic;

Component My_And --template of My_And described above
 Port(A, B  : in std_logic;
      ANDED : OUT std_logic);  
end component;

begin

UUT: My_And Port Map (Ax, Bx, ANDout);
--Ax maps to A, Bx maps to Bx and ANDout maps to ANDED

Process
begin
  wait for 30 ns; -- so Ax = 0, Bx = 0 for 30 ns
  Ax <= '0';  
  Bx <= '1';
  wait for 30 ns; -- so Ax = 0, Bx = 1 for 30 ns
  Ax <= '1';  
  Bx <= '0';
  wait for 30 ns; -- so Ax = 1, Bx = 0 for 30 ns
  Ax <= '1';  
  Bx <= '1';
  wait for 30 ns; -- so Ax = 1, Bx = 1 for 30 ns
  Ax <= '0';  
  Bx <= '0'; --will go back to the start of the process
end process;

end;