clock source for CPLD/FPGA, any suggestion?

[marcelino]

possible din na yung logic gates mismo ang mabagal..
nag-try ako dati ng 16MHz, 'di na talaga kinaya nung HC04.

more likely.... kaya nga etong 3.579545M nalang. mabilis na din naman to para sa mga experiments ko... at sa ganito kabilis, pwede na na din alisin yung schmitt....

ang CPLD kit from e-gizmo, could handle division up to 16 naman.

[insomartin]

subscribing!

[ckiana02]

   There are a lot of 3.3V crystal oscillators available in RS Phil from Php106 (1.8 MHz) to Php152 (50 MHz) SMT packaging.  These oscillators are ideal for CPLDs/FPGAs.

[marcelino]

   There are a lot of 3.3V crystal oscillators available in RS Phil from Php106 (1.8 MHz) to Php152 (50 MHz) SMT packaging.  These oscillators are ideal for CPLDs/FPGAs.

Thank you sir for the info. papano po paggamitin nun? we simply power it up then, ok na? clock and gnd nalang ang ikakabit sa CPLD?

you are referring to something like this, diba?
http://philippines.rs-online.com/web/search/searchBrowseAction.html?method=getProduct&R=6720551

[rdpzycho]

yup sis.

[ckiana02]

yes 

[marcelino]

awww...... meron palang ganyan!!! heheh

thank you!

[Born2BeWired]

ano bandwidth nung scope na gamit mo sis?

malapit na sa boundary ng most basic logic gates 'yung 30MHz. 'yung iba topped na at 25MHz ata.

Sir RD is right. LSTTL gates will have a hard time catching up with a 30MHz signal, as their rise and fall times will exceed the slope of a 30MHz signal. Looking at this in the frequency domain, the LSTTL inability to process >30MHz signal will make it behave like a low pass filter, suppressing the harmonics of the 30MHz squarewave. A square wave stripped off its harmonics is a sine wave.  This effect is very similar to the slewing effect of an OPAMP, albeit occuring at a much lower frequency.

madyo malupit din ang overshoot at undershoot.

Welcome to the world of high speed electronics . What you see are signal reflections caused by the stray reactance of your PCB traces, which acts essentially like a mismatched transmission line. This is the price you have to pay for owning a wide bandwidth oscilloscope, makikita mo na ang mga bagay bagay na magpapagulo sa isip mo.

[marcelino]

Welcome to the world of high speed electronics . What you see are signal reflections caused by the stray reactance of your PCB traces, which acts essentially like a mismatched transmission line. This is the price you have to pay for owning a wide bandwidth oscilloscope, makikita mo na ang mga bagay bagay na magpapagulo sa isip mo.

hehehe... yan na nga siguro ang nangyayari... siguro malaki pa ang effect kasi sa vero board ko lang ginawa.

for instance dito sa same experiment ko, nilagyan ko ng 3.3V, pero ang maximum voltage (caused by overshoot) na nababasa nasa 4.2V.

makakasira na kaya to ng PLD ko? di ko pa naman tinitignan masyado ang internal construction ng CPLD, pero sana may clipping na mangyayari tulad ng sa MCUs.

Di ko pa naman kinakabit sa PLD mismo.

[rdpzycho]

kung pa-konti konti lang sis, 'di pa naman.

sakit talaga sa ulo ang high frequency, lalo na 'yung may binubutingting ka on-the-fly tapos biglang umayos ang response, kailangan mo tuloy gawan ng paraan 'yung hinahawakan mo.

[marcelino]

kung pa-konti konti lang sis, 'di pa naman.

sakit talaga sa ulo ang high frequency, lalo na 'yung may binubutingting ka on-the-fly tapos biglang umayos ang response, kailangan mo tuloy gawan ng paraan 'yung hinahawakan mo.

hehehe... buti nalang nagagawan mo ng paraan. kung hindi kasama ka na nung product!
example nito yung first time ko sa MCU, nakalimutan ko ang caps to the ground sa xtal... nung nahawakan ko, nagblink yung LED!!!

marami pa talgang matutunan at aaralin sa paligid-ligid!

so OK lang pala yun... sige. try ko bukas.

[insomartin]

OT scenario....

sir hawakan nyo daw po sa ilalim nang enclosure, me butas jan para sa daliri nyo...

: i miss my FM transmitter. dapat nakatayo ko sa left side nang circuit ko. hahaha.

[rdpzycho]